Abstract : In present day almost all FPGA and ASIC in every application PLL are the part of the chip. With any variation in PLL frequency the complete performance of the design would be affected. At Deep Submicron technology nodes threshold voltage Vth shift will happen at different corners due to manufacturing process. When designer squeezes to achieve maximum performance and low voltage, the shift in Vth impacts the complete circuit/chip performance in addition to temperature variation. Present day applications like medical, wireless and handheld require maximum battery like with efficient and effective. Multiple process corner analysis and characterization of library and circuit is introduced to analyze and evaluate the effective performance at the process corners under varied conditions. These corner analysis results are useful in circuit design to optimize supply voltage requirement and minimum and maximum threshold voltage at which a specific application operating conditions. Library Characterization and corner analysis results show that operation at the optimal Vdd-Vth voltage levels can lead to an effective design to save energy to a larger magnitude. Also additional analysis into threshold voltage and variations due to temperature will provide more insight in to the process variation behavior of MOSFET circuit. The process variation impacts technical and economically during manufacturing, especially with reference to wafer yield in turn product yield, reliability of the product. Early analysis of variations and its effect allow designer to analyze and enhance performance by compensatory circuits, yield, and reliability due to variations. This design work is carried out using BSIM4.X MOSFET models to analyze the performance due to process variation.