[This article belongs to Volume - 56, Issue - 03]
Gongcheng Kexue Yu Jishu/Advanced Engineering Science
Journal ID : AES-05-04-2024-690

Title : Design of Efficient and optimized Multiply-Accumulate Unit Using Convolutional Neural Networks in DSP Applications
Manjula B Bhajantri, Dr. Sharanabasaveshwar G Hiremath,

Abstract : CNNs find application across various machine learning tasks, including voice, image, and video processing. With the increasing demand for quicker response times in real-time applications, there's a growing necessity for rapid implementation of CNNs. Nevertheless, the computational demands of the convolutional layer in CNNs result in increased processing delays. Hence, this research aims to develop a streamlined and swift convolution block tailored for the hardware execution of the CNN valid algorithm. The proposed solution uses a optimized Multiplier and Accumulator (MAC) unit that incorporates a modified conventional multiplier Reduction to achieve time optimization. The MAC, crucial to the convolution process, is meticulously optimized for rapidity. This architecture occupies an area of 7654 nm, consumes 154468.306 nw of power, and operates with a timing of 6367.776 ps. Consequently, the proposed architecture excels in power efficiency without compromising on other parameters like area and delay. The MAC architecture is crafted using Verilog, with its code's testbench verified and simulated in Cadence NCSIM, while synthesis is conducted through Cadence's Genus tool.