[This article belongs to Volume - 54, Issue - 06]
Gongcheng Kexue Yu Jishu/Advanced Engineering Science
Journal ID : AES-04-08-2022-259

Title : High-Speed Pipelined Architecture-Based Residue Number System For FIR Filter Design
M Balaji, N Padmaja,

Abstract : The Residue Number System has acquired importance in recent years due to its carry-free propagation, and parallelism. This paper reviews the additional capabilities of usage of alternative moduli sets, forward converters and reverse converters, etc can help in speeding up the design. The less area can be obtained by carry-save adder or carry propagate adder. Also the less area and delay with modular multipliers using booth multipliers, fast multipliers like Dadda multipliers, etc. Further, these are modified for multi-value RNS systems like ternary and Quarternary RNS. The designs can be encoded with different encoding mechanisms like thermometer codes, one hot code, binary codes, etc. The designs are enhanced in speed with distributed architecture and related modifications. The designs are evaluated for various parameters like area, delay, power, power delay product, energy-delay product, the maximum frequency of operation, order of filters, number of taps, minimum period cycle, energy per sample, etc. Among the RNS Filters developed, the complexity increases as the number of taps are increased and multi-value systems are used. The RNS FIR Filter with pipelining has improved significantly the performance of the filter. The proposed distributed arithmetic-based FIR Filter with pipelining has produced the least delay with improvement by 21.5% to 88.54%, which is more advantage in designing fast DSP applications.